The present invention is directed to an integrated circuit. One embodiment includes a semiconductor memory device having a plurality of memory cells.
A conventional flash memory is formed by a matrix of flash transistors. The matrix includes rows and columns of flash transistors. These transistors are also called EEPROM transistors, which is an abbreviation for the term electronically erasable programmable read-only memory. The flash memory is a non-volatile memory. This means that stored information is maintained, even if the energy supply to the memory cells is turned off. The memory content may be programmed using electrical pulses.
The flash transistors are field effect transistors (FET), which include a floating gate. The floating gate consists of a conductor surrounded by insulators. Therefore, the charge carriers deposited on the floating gate my not dissipate. The conductor is positioned above the source-drain-channel of the flash transistor. The memory cell is programmed by applying charges to the floating gate or by discharging the floating gate. Due to the charge deposited on the floating gate, a voltage is provided, which increases or decreases the channel between the source and drain of the transistor. Consequently, the voltage of the floating gate influences the conductivity of the source-gate-channel.
The plurality of sectors defined on the flash memory is called the sectorization of the memory cell. The size of a sector defines the speed of erasing and programming of the memory cells. In general, the size of the sectors is adapted to the user's needs of both small and big sectors depending on the target application of the flash memory. In order to have different sector sizes the flash memory must be completely redesigned. Therefore, additional costs are conferred onto the flash memory.
For these and other reasons, there is a need for the present invention.